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LMP92018 Datasheet(PDF) 9 Page - Texas Instruments |
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LMP92018 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 33 page  D23 D0 SCLK DIN t3 t1 1 PD23 PD0 DOUT t8 PD0 CSB 2 t2 D1 PD1 24 23 PD22 D22 70% 30% t11 70% 70% 70% 70% tr tf LMP92018 www.ti.com SNAS514B – NOVEMBER 2011 – REVISED MAY 2013 Electrical Characteristics (continued) Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over the temperature range of −30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output CL = 200 pF unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units tCONV Temperature Conversion Time 25.85 ms SPI TIMING CHARACTERISTICS SPI Clock Period during ADC t1 178 12500 ns data access SPI Clock Period during t1 178 5000 ns Temperature Sensor access SPI Clock Period for all t1 transactions not involving ADC or 100 ns Temperature Sensor tr SCLK Rise Time 2 ns tf SCLK Fall Time 2 ns t2 SCLK HIGH Time 8 ns t3 SCLK LOW Time 8 ns CSB set-up time to SCLK falling t4 5 ns edge t5 DIN Set-up time 5 ns t6 DIN Hold time 4 ns CSB hold time after 24th falling t7 10 ns edge of SCLK t8 CSB High Pulse Width 30 ns CL=30pF, VIO=1.8 10 DOUT hold time after SCLK tDH ns Rising Edge CL=30pF, 3V≤VIO≤5.25V 5 DOUT Delay after SCLK Rising tDD CL=30pF 40 ns Edge SCLK Delay after CSB Rising t11 3 ns Edge CSB Rising Edge to DOUT TRI- tDOZ 4 10 ns STATE tZDO CSB Falling Edge to DOUT active sink/source 200uA, CL=150pF 5 14 ns SPI Interface Timing Diagram Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LMP92018 |
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