2001 Feb 02

10

NXP Semiconductors

Product specification

Low-cost stereo filter DAC

UDA1330ATS

handbook, full pagewidth

tstp(L3)

address

L3DATA

L3CLOCK

L3MODE

address

data byte #1

data byte #2

MGL725

Fig.6 Multibyte data transfer.

Programming the features

When the data transfer of type ‘status’ is selected, the features for the system clock frequency and the data input format

can be controlled.

Table 6

Data transfer of type ‘status’

When the data transfer of type ‘data’ is selected, the features for volume, de-emphasis and mute can be controlled.

Table 7

Data transfer of type ‘data’

BIT7

BIT6

BIT5

BIT4

BIT 3

BIT2

BIT1

BIT0

REGISTER SELECTED

0

0

SC1

SC0

IF2

IF1

IF0

0

SC = system clock frequency (2 bits); see Table 8

IF = data input format (3 bits); see Table 9

1

000

000

0

not used

BIT7

BIT6

BIT5

BIT4

BIT 3

BIT2

BIT1

BIT0

REGISTER SELECTED

0

0

VC5

VC4

VC3

VC2

VC1

VC0

VC = volume control (6 bits); see Table 11

0

100

000

0

not used

1

0

0

DE1

DE0

MT

0

0

DE = de-emphasis (2 bits); see Table 10

MT =mute (1bit); seeTable 12

1

100

000

1

default setting