HIP4086, HIP4086A

3

FN4220.10

March 27, 2015

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Pin Configuration

HIP4086, HIP4086A

(24 LD PDIP, SOIC)

TOP VIEW

1

BHB

2

BHI

3

BLI

4

ALI

5

AHI

6

VSS

7

RDEL

8

UVLO

9

RFSH

10

DIS

11

CLI

12

CHI

24

BHO

23

BHS

22

BLO

21

ALO

20

VDD

19

CLO

18

AHS

17

AHO

16

AHB

15

CHS

14

CHO

13

CHB

Pin Descriptions

PIN NUMBER

SYMBOL

DESCRIPTION

16

1

13

AHB

BHB

CHB

(xHB)

High-Side Bias Connections. One external bootstrap diode and one capacitor are required for

each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB

pin.

18

23

15

AHS

BHS

CHS

(xHS)

High-Side Source Connections. Connect the sources of the high-side power MOSFETs to these

pins. The negative side of the bootstrap capacitors are also connected to these pins.

5

2

12

AHI

BHI

CHI

(xHI)

High-Side Logic Level Inputs. Logic at these three pins controls the three high-side output

drivers, AHO (Pin 17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI

is high, xHO is low. Unless the dead time is disabled by connecting RDEL (Pin 7) to ground, the

low-side input of each phase will override the corresponding high side input on that phase -

see “Truth Table” on page 2. If RDEL is tied to ground, dead time is disabled and the outputs

follow the inputs with no shoot-thru protection. DIS (Pin 10) also overrides the high-side inputs.

4

3

11

ALI

BLI

CLI

(xLI)

Low-Side Logic Level Inputs. Logic at these three pins controls the three low-side output

drivers ALO (Pin 21), BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the

lower inputs control both xLO and xHO drivers, with the dead time set by the resistor at RDEL

(Pin 7). DIS (Pin 10) high level input overrides xLI, forcing all outputs low. xLI can be driven by

6

VSS

Ground. Connect the sources of the low-side power MOSFETs to this pin.

7

RDEL

the dead time between drivers - see Figure 18. All drivers turn off with minimal delay, RDEL

both upper and lowers can be commanded on simultaneously. While not necessary in most

applications, a decoupling capacitor of 0.1µF or smaller may be connected between RDEL and

8

UVLO

undervoltage set point - see Figure 19. With this pin not connected, the under voltage disable

9

RFSH

the length of the start up refresh pulse - see Figure 17. If this pin is not connected, the refresh

pulse is typically 1.5µs.

10

DIS

Disable Input. Logic level input that when taken high sets all six outputs low. DIS high

overrides all other inputs. With DIS low, the outputs are controlled by the other inputs. DIS can