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ISL6140CBZ-T Datasheet(PDF) 2 Page - Intersil Corporation |
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ISL6140CBZ-T Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 19 page 2 FN9039.4 Pin Configuration ISL6140, ISL6150 (8 LD SOIC) TOP VIEW ISL6140 has active Low (L version) PWRGD output pin ISL6150 has active High (H version) PWRGD output pin Pin Description PWRGD (ISL6140; L Version) Pin 1 This digital output is an open-drain pull-down device. The Power Good comparator looks at the DRAIN pin voltage compared to the internal VPG reference (VPG is nominal 1.7V); this essentially measures the voltage drop across the external FET and sense resistor. If the voltage drop is small (<1.7V is normal), the PWRGD pin pulls low (to VEE); this can be used as an active low enable for an external module. If the voltage drop is too large (>1.7V indicates some kind of short or overload condition), the pull-down device shuts off, and the pin becomes high impedance. Typically, an external pull-up of some kind is used to pull the pin high (many brick regulators have a pull-up function built in). PWRGD (ISL6150; H Version) Pin 1 This digital output is a variation of an open-drain pull-down device. The power good comparator is the same as described above, but the polarity of the output is reversed, as follows: If the voltage drop across the FET is too large (>1.7V), the open drain pull-down device will turn on, and sink current to the DRAIN pin. If the voltage drop is small (<1.7V), a 2nd pull-down device in series with a 6.2k resistor (nominal) sinks current to VEE; if the external pull-up current is low enough (<1mA, for example), the voltage drop across the resistor will be big enough to look like a logic high signal (in this example, 1mA*6.2kΩ = 6.2V). This pin can thus be used as an active high enable signal for an external module. OV VEE 5 7 6 4 3 2 GATE DRAIN UV SENSE PWRGD/PWRGD 1 VDD 8 Ordering Information PART NUMBER (Notes 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL6140CBZ ISL61 40CBZ 0 to +70 8 Ld SOIC (Pb-Free) M8.15 ISL6140CBZ-T (Note 1) ISL61 40CBZ 0 to +70 8 Ld SOIC (Pb-Free) M8.15 ISL6140IBZ-T (Note 1) ISL61 40IBZ -40 to +85 8 Ld SOIC (Pb-Free) M8.15 ISL6140IBZ ISL61 40IBZ -40 to +85 8 Ld SOIC (Pb-Free) M8.15 ISL6150CB ISL 6150CB 0 to +70 8 Ld SOIC M8.15 ISL6150CBZ ISL61 50CBZ 0 to +70 8 Ld SOIC (Pb-Free) M8.15 ISL6150CBZ-T (Note 1) ISL61 50CBZ 0 to +70 8 Ld SOIC (Pb-Free) M8.15 ISL6150IB-T (Note 1) ISL 6150IB 0 to +70 8 Ld SOIC M8.15 ISL6150IBZ ISL61 50IBZ -40 to +85 8 Ld SOIC (Pb-Free) M8.15 ISL6150IBZ-T (Note 1) ISL61 50IBZ -40 to +85 8 Ld SOIC (Pb-Free) M8.15 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page forISL6140. For more information on MSL please see techbrief TB363. ISL6140, ISL6150 |
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Similar Description - ISL6140CBZ-T |
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