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ISL6173EVAL3 Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6173EVAL3 Datasheet(HTML) 10 Page - Intersil Corporation |
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10 / 20 page  10 FN9186.3 January 3, 2006 automatically retries to turn on the MOSFET after a wait period, during which CT is charged and discharged 64 times and the retry attempt takes place on the 65th time. This wait period allows the MOSFET junction to cool down. 2. Way Overcurrent (WOC) Mode - This mode is designed to handle very fast, very low impedance shorts on the load side, which can result in very high di/dt. Typically, the current limit set for this mode is 300% of the current regulation limit. This mode uses a very fast comparator, which directly looks at the voltage drop across RSNS and pulls the gate very quickly to GND (as shown in Figure 14) and immediately releases it. If the WOC is still present, the IC enters current regulation mode and the rest of the current regulation behavior follows as described earlier in undercurrent regulation mode. Additionally, as shown in the block diagram, there is also an “OC comparator”, which also looks at the Rsense voltage drop. When this drop exceeds the Current Limit set point, it triggers the timeout circuit, which starts ticking and CTx is allowed to charge. If the current limit condition remains in effect until after the time-out period expires (CTx voltage exceeding 1.178V), the gate of the MOSFET is pulled down, the SSx capacitor is discharged, FLT is asserted and a new SS sequence is allowed to begin after ENx recycle or by keeping the RTR/LTCH pin pulled low. The voltage on OCREF pin is the same as the internal band- gap reference voltage, which is 1.178V (nominal). A resistor to GND from this pin sets the reference current (and hence the reference voltage) for the current limit amplifier and OC/WOC comparators. The current regulation (CR) duration is set by the capacitor on CT pin to GND. Once the voltage on this pin reaches 1.178V, the CR duration expires. Fault (FLT) pin goes active (pulls low), signaling the load of a fault condition and the gate (GT) pin gets pulled low. Retry vs Latched Fault Operational Modes: RTR/LTCH pin dictates the IC behavior after the gate (GT) pin pulls down following OC timeout expiration. If the RTR/LTCH pin is left floating, the gate pin will remain latched off. It can only be released by de-asserting and reasserting the enable (EN) input. If RTR/LTCH pin is pulled to GND, then the Retry mode will be activated. In this mode the IC will automatically attempt to turn-on the MOSFET after a delay, determined by the capacitor on CT pin. In the Retry mode, the internal logic charges and discharges the CT cap 64 times during “wait” period. On the 65th time, the FLT output clears during retry attempt. If the overcurrent condition persists after the soft-start, the CT pin will again start charging and the process repeats. Bias and Charge Pump Voltages: The BIAS pin feeds the chip bias voltage directly to the first of the two internal charge pumps, which are cascaded. The output of the first charge pump, in addition to feeding the second charge pump, is accessible on the CPVDD pin. The voltage on the CPVDD pin is approximately 5V. It also provides power to the POR and band-gap circuitry as shown in the block diagram. A capacitor connected externally across CPQ+ and CPQ- pins of the IC is the “flying” cap for the charge-pump. The second charge-pump is used exclusively to drive the gates of the MOSFETs through the 24µA current sources, one for each channel. The output of this charge pump is approximately 10V as shown in the block diagram. Tracking Q Rsns 3K Rset - + Io Iset Vin Vo + - + - ISL6173 25 Ω WOC COMPARATOR GATE PULLDOWN CURRENT FIGURE 14. WOC OPERATION CH1: VO1, CH2: VO2, T = 2ms/DIV, CSS = 0.066µF FIGURE 15. TRACKING MODE WAVEFORMS ISL6173 |
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