11

FN9107.3

June 30, 2005

Active, Deep Sleep and Deeper Sleep Modes

The ISL6217A Multi-Phase Controller is designed to control

the CORE output voltage as per the IMVP-IV™ and

IMVP-IV+™ specifications for Active, Deep Sleep, and

Deeper Sleep Modes of Operation.

After initial Start-up, a logic high signal on DSEN# and a

logic low signal on DRSEN signals the ISL6217A to operate

in Active mode. Refer to Table 2. This mode will recognize

VID code changes and regulate the output voltage to these

command voltages.

TABLE 2. OUTPUT VOLTAGE AS A FUNCTION OF DSEN#

AND DRSEN LOGIC STATES

DSEN# -

STP_CPU#

DRSEN -

DPRSLPVR

MODE OF

OPERATION

OUTPUT

VOLTAGE

1

0

Active

VID

0

0

Deep Sleep

DSV

0

1

Deeper Sleep

DRSV

1

1

Deeper Sleep

DRSV

FIGURE 5. PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING

FIGURE 6. VCORE RESPONSE FOR DEEPER SLEEP COMMAND

FIGURE 7. VCORE RESPONSE FOR DEEPER SLEEP COMMAND

VID[0..5]

New VID Code

Current VID Code

Current Voltage Level

New Voltage Level

V

CC_CORE

PGOOD

<600ns

HIGH

VID[0..5]

VID Code remains the same

V

CC_CORE

<30us

STP_CPU#

(DSEN#)

V

Deep Sleep

VID Command Voltage

VID[0..5]

VID Code remains the same

V

CC_CORE

STP_CPU#

(DSEN#)

V

Deeper Sleep

DPRSLPVR

(DRSEN)

Deeper Sleep Mode

Short DPRSLP causes

V

V

Deep Sleep

ISL6217A