4

Applying the HA-4900 Series Comparators

Supply Connections

This device is exceptionally versatile in working with most available

power supplies. The voltage applied to the V+ and V- terminals

determines the allowable input signal range; while the voltage applied

dual analog supplies are available, these would be connected to V+

and V-, while the logic supply and return would be connected to

be connected together at one point in the system, since the comparator

is immune to noise on the logic supply ground. A negative output

obtained using dual supplies. In systems where only a single logic

grounded. If an input signal could swing negative with respect the V-

terminal, a resistor should be connected in series with the input to limit

input current to < 5mA since the C-B junction of the input transistor

would be forward biased.

Unused Inputs

Inputs of unused comparator sections should be tied to a differential

voltage source to prevent output “chatter.”

Crosstalk

Simultaneous high frequency operation of all other channels in the

package will not affect the output logic state of a given channel,

provided that its differential input voltage is sufficient to define a

given logic state (

ΔV

input lines should be shielded from other signal sources to reduce

crosstalk and interference.

Power Supply Decoupling

Decouple all power supply lines with 0.01

μF ceramic capacitors to

ground line located near the package to reduce coupling between

channels or from external sources.

Response Time

Fast rise time (<200ns) input pulses of several volts amplitude may

result in delay times somewhat longer than those illustrated for

100mV steps. Operating speed is optimized by limiting the

maximum differential input voltage applied, with resistor-diode

clamping networks.

Typical Applications

Data Acquisition System

In this circuit the HA-4900 series is used in conjunction with a D

to A converter to form a simple, versatile, multi-channel analog

input for a data acquisition system. In operation the processor first

sends an address to the D to A, then the processor reads the digital

word generated by the comparator outputs. To perform a simple

comparison, the processor sets the D to A to a given reference

level, then examines one or more comparator outputs to determine

if their inputs are above or below the reference. A window

comparison consists of two such cycles with 2 reference levels set

by the D to A. One way to digitize the inputs would be for the

processor to increment the D to A in steps. The D to A address, as

each comparator switches, is the digitized level of the input. While

stairstepping the D to A is slower than successive approximation,

all channels are digitized during one staircase ramp.

Schematic Diagram

BIAS 2

ONE FOURTH ONLY

1k

Ω

1k

Ω

1k

Ω

1k

Ω

1k

Ω

BIAS 1

540

Ω

200k

Ω

4k

Ω

4k

Ω

BIAS 3

BIAS 4

+IN

500

Ω

13k

Ω

1k

Ω

1k

Ω

-IN

2.5k

Ω

2.5k

Ω

360

Ω

664

Ω

19k

Ω

5k

Ω

8k

Ω

8k

Ω

100

Ω

14k

Ω

100

Ω

8k

Ω

OUT

V-

V+

HA-4900, HA-4902, HA-4905