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SM320C6678-HIREL Datasheet(PDF) 8 Page - Texas Instruments |
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SM320C6678-HIREL Datasheet(HTML) 8 Page - Texas Instruments |
8 / 244 page SM320C6678-HIREL SPRS910A—November 2010—Revised August 2013 8 Contents Copyright 2014 Texas Instruments Incorporated Submit Documentation Feedback 7.6.1 Main PLL Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.6.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . 144 7.6.3 Main PLL Control Register . . . . . . . . . . . . . . . . . . . . 151 7.6.4 Main PLL and PLL Controller Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.6.5 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing . . . . . . . . . . . 152 7.7 DD3 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.7.1 DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . 154 7.7.2 DDR3 PLL Device-Specific Information . . . . . . . . 155 7.7.3 DDR3 PLL Initialization Sequence. . . . . . . . . . . . . 155 7.7.4 DDR3 PLL Input Clock Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7.8 PASS PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 7.8.1 PASS PLL Control Register . . . . . . . . . . . . . . . . . . . . 157 7.8.2 PASS PLL Device-Specific Information . . . . . . . . 158 7.8.3 PASS PLL Initialization Sequence . . . . . . . . . . . . . 158 7.8.4 PASS PLL Input Clock Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 7.9 Enhanced Direct Memory Access (EDMA3) Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 7.9.1 EDMA3 Device-Specific Information . . . . . . . . . . 161 7.9.2 EDMA3 Channel Controller Configuration . . . . 161 7.9.3 EDMA3 Transfer Controller Configuration. . . . . 161 7.9.4 EDMA3 Channel Synchronization Events. . . . . . 162 7.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.10.1 Interrupt Sources and Interrupt Controller . . . 166 7.10.2 CIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.10.3 Inter-Processor Register Map. . . . . . . . . . . . . . . . 189 7.10.4 NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 7.10.5 External Interrupts Electrical Data/Timing . . . 191 7.10.6 Host Interrupt Output. . . . . . . . . . . . . . . . . . . . . . . 192 7.11 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . 193 7.11.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 7.11.2 MPU Programmable Range Registers . . . . . . . . 201 7.12 DDR3 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . 206 7.12.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 7.12.2 DDR3 Memory Controller Race Condition Consideration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 7.12.3 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 7.13 I2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 7.13.1 I2C Device-Specific Information . . . . . . . . . . . . . .208 7.13.2 I2C Peripheral Register Description(s) . . . . . . . .209 7.13.3 I2C Electrical Data/Timing. . . . . . . . . . . . . . . . . . . .210 7.14 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 7.14.1 SPI Electrical Data/Timing. . . . . . . . . . . . . . . . . . . .213 7.15 HyperLink Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 7.15.1 HyperLink Device-Specific Interrupt Event. . . .216 7.15.2 HyperLink Electrical Data/Timing . . . . . . . . . . . .218 7.16 UART Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 7.17 PCIe Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 7.18 TSIP Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 7.18.1 TSIP Electrical Data/Timing . . . . . . . . . . . . . . . . . .222 7.19 EMIF16 Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 7.19.1 EMIF16 Electrical Data/Timing . . . . . . . . . . . . . . .224 7.20 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 7.21 Security Accelerator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 7.22 Gigabit Ethernet (GbE) Switch Subsystem. . . . . . . . . .227 7.23 Management Data Input/Output (MDIO) . . . . . . . . . .229 7.24 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 7.24.1 Timers Device-Specific Information . . . . . . . . . .230 7.24.2 Timers Electrical Data/Timing . . . . . . . . . . . . . . . .231 7.25 Serial RapidIO (SRIO) Port . . . . . . . . . . . . . . . . . . . . . . . . .231 7.26 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . .232 7.26.1 GPIO Device-Specific Information . . . . . . . . . . . .232 7.26.2 GPIO Electrical Data/Timing. . . . . . . . . . . . . . . . . .232 7.27 Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 7.28 Emulation Features and Capability . . . . . . . . . . . . . . . .233 7.28.1 Advanced Event Triggering (AET) . . . . . . . . . . . .233 7.28.2 Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 7.28.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 9 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 9.1 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 9.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 |
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