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TMS320C55 Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320C55 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 159 page  TMS320C5515 SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013 www.ti.com 2.2.2 On-Chip Single-Access RAM (SARAM) The SARAM is located at the byte address range 010000h – 04FFFFh and is composed of 32 blocks of 4K words each (see Table 2-3). Each SARAM block can perform one access per cycle (one read or one write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed by the USB and LCD DMA buses. Table 2-3. SARAM Blocks CPU DMA/USB CONTROLLER MEMORY BLOCK BYTE ADDRESS RANGE BYTE ADDRESS RANGE 010000h − 011FFFh 0009 0000h – 0009 1FFFh SARAM 0 012000h − 013FFFh 0009 2000h – 0009 3FFFh SARAM 1 014000h − 015FFFh 0009 4000h – 0009 5FFFh SARAM 2 016000h − 017FFFh 0009 6000h – 0009 7FFFh SARAM 3 018000h − 019FFFh 0009 8000h – 0009 9FFFh SARAM 4 01A000h − 01BFFFh 0009 A000h – 0009 BFFFh SARAM 5 01C000h − 01DFFFh 0009 C000h – 0009 DFFFh SARAM 6 01E000h − 01FFFFh 0009 E000h – 0009 FFFFh SARAM 7 020000h − 021FFFh 000A 0000h – 000A 1FFFh SARAM 8 022000h − 023FFFh 000A 2000h – 000A 3FFFh SARAM 9 024000h − 025FFFh 000A 4000h – 000A 5FFFh SARAM 10 026000h − 027FFFh 000A 6000h – 000A 7FFFh SARAM 11 028000h − 029FFFh 000A 8000h – 000A 9FFFh SARAM 12 02A000h − 02BFFFh 000A A000h – 000A BFFFh SARAM 13 02C000h − 02DFFFh 000A C000h – 000A DFFFh SARAM 14 02E000h − 02FFFFh 000A E000h – 000A FFFFh SARAM 15 030000h − 031FFFh 000B 0000h – 000B 1FFFh SARAM 16 032000h − 033FFFh 000B 2000h – 000B 3FFFh SARAM 17 034000h − 035FFFh 000B 4000h – 000B 5FFFh SARAM 18 036000h − 037FFFh 000B 6000h – 000B 7FFFh SARAM 19 038000h − 039FFFh 000B 8000h – 000B 9FFFh SARAM 20 03A000h − 03BFFFh 000B A000h – 000B BFFFh SARAM 21 03C000h − 03DFFFh 000B C000h – 000B DFFFh SARAM 22 03E000h − 03FFFFh 000B E000h – 000B FFFFh SARAM 23 040000h – 041FFFh 000C 0000h – 000C 1FFFh SARAM 24 042000h – 043FFFh 000C 2000h – 000C 3FFFh SARAM 25 044000h – 045FFFh 000C 4000h – 000C 5FFFh SARAM 26 046000h – 047FFFh 000C 6000h – 000C 7FFFh SARAM 27 048000h – 049FFFh 000C 8000h – 000C 9FFFh SARAM 28 04A000h – 04BFFFh 000C A000h – 000C BFFFh SARAM 29 04C000h – 04DFFFh 000C C000h – 000C DFFFh SARAM 30 04E000h – 04FFFFh 000C E000h – 000C FFFFh SARAM 31(1) (1) SARAM31 (byte address range: 0x4E000 – 0x4EFFF) is reserved for the bootloader. After the boot process is complete, this memory space can be used. 2.2.3 On-Chip Read-Only Memory (ROM) The zero-wait-state ROM is located at the byte address range FE0000h – FFFFFFh. The ROM is composed of four 16K-word blocks, for a total of 128K bytes of ROM. The ROM address space can be mapped by software to the external memory or to the internal ROM. The standard device includes a Bootloader program resident in the ROM. 10 Device Overview Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5515 |
Similar Part No. - TMS320C55_15 |
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Similar Description - TMS320C55_15 |
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