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ISL6608CB Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6608CB Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 11 page 9 Power Dissipation Package power dissipation is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125°C. The maximum allowable IC power dissipation for the SO-8 package is approximately 800mW. When designing the driver into an application, it is recommende d that the following calculation be performed to ensure safe operation at the desired frequency for the selected MOSFETs. The power dissipated by the driver is approximated as below and plotted as in Figure 9. where fsw is the switching frequency of the PWM signal. VU and VL represent the upper and lower gate rail voltage. QU and QL are the upper and lower gate charge determined by MOSFET selection and any external capacitance added to the gate pins. The IDDQ VCC product is the quiescent power of the driver and is typically negligible. Layout Consideration For heat spreading, place copper underneath the IC whether it has an exposed pad or not. The copper area can be extended beyond the bottom area of the IC and/or connected to buried copper plane(s) with thermal vias. This combination of vias for vertical heat escape, extended copper plane, and buried planes for heat spreading allows the IC to achieve its full thermal potential. Place each channel power component as close to each other as possible to reduce PCB copper losses and PCB parasitics: shortest distance between DRAINs of upper FETs and SOURCEs of lower FETs; shortest distance between DRAINs of lower FETs and the power ground. Thus, smaller amplitudes of positive and negative ringing are on the switching edges of the PHASE node. However, some space in between power components is required for good airflow. The gate traces from the drivers to the FETs should be kept short and wide to reduce the inductance of the traces and promote clean drive signals. Pfsw 1.5VUQU VLQL + () I DDQVCC + = FIGURE 9. POWER DISSIPATION vs FREQUENCY FREQUENCY (kHz) 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 QU=50nC QL=50nC QU=50nC QL=100nC QU=100nC QL=200nC QU=20nC QL=50nC ISL6608 |
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