6

FN9221.2

April 27, 2009

Functional Pin Description

Note: Pin numbers refer to the SOIC package. Check

diagram for corresponding QFN pinout.

UGATE (Pin 1)

Upper gate drive output. Connect to gate of high-side

N-Channel power MOSFET. A gate resistor is never

recommended on this pin, as it interferes with the operation

shoot-through protection circuitry.

BOOT (Pin 2)

Floating bootstrap supply pin for the upper gate drive.

Connect a bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge

used to turn on the upper MOSFET. See “Bootstrap

Considerations” on page 7 for guidance in choosing the

appropriate capacitor value.

PWM (Pin 3)

The PWM signal is the control input for the driver. The PWM

signal can enter three distinct states during operation, see

“Three-State PWM Input” on page 7 for further details. Connect

this pin to the PWM output of the controller.

GND (Pin 4)

Ground pin. All signals are referenced to this node.

LGATE (Pin 5)

Lower gate drive output. Connect to gate of the low side

N-Channel power MOSFET. A gate resistor is never

recommended on this pin, as it interferes with the operation

shoot-through protection circuitry.

VCC (Pin 6)

Connect this pin to a +5V bias supply. Locally bypass with a

high quality ceramic capacitor to ground.

EN (Pin 7)

Enable input pin. Connect this pin high to enable and low to

disable the driver.

PHASE (Pin 8)

Connect this pin to the source of the upper MOSFET. This

pin provides the return path for the upper gate driver current.

Thermal Pad (in QFN only)

The metal pad underneath the center of the IC is a thermal

substrate. The PCB “thermal land” design for this exposed

die pad should include vias that drop down and connect to

one or more buried copper plane(s). This combination of

vias for vertical heat escape and buried planes for heat

spreading allows the QFN to achieve its full thermal

potential. This pad should be either grounded or floating,

and it should not be connected to other nodes. Refer to

TB389 for design guidelines.

UGATE Turn-On Propagation Delay

-

18

-

ns

LGATE Turn-On Propagation Delay

-

23

-

ns

Three-state to UG/LG Rising Propagation

Delay

-

20

-

ns

OUTPUT

Upper Drive Source Resistance

250mA Source Current

-

1.0

2.5

Ω

Upper Drive Sink Resistance

250mA Sink Current

-

1.0

2.5

Ω

Lower Drive Source Resistance

250mA Source Current

-

1.0

2.5

Ω

Lower Drive Sink Resistance

250mA Sink Current

-

0.4

1.0

Ω

NOTE:

4. Limits established by characterization and are not production tested

Electrical Specifications

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ISL6609, ISL6609A