8

FN9160.4

May 5, 2008

Description

Operation

Designed for versatility and speed, the ISL6614A MOSFET

driver controls both high-side and low-side N-Channel FETs of

two half-bridge power trains from two externally provided PWM

signals.

Prior to VCC exceeding its POR level, the Pre-POR

overvoltage protection function is activated during initial startup;

the upper gate (UGATE) is held low and the lower gate

(LGATE), controlled by the Pre-POR overvoltage protection

circuits, is connected to the PHASE. Once the VCC voltage

surpasses the VCC Rising Threshold (See “Electrical

Specifications” table on page 5), the PWM signal takes control

of gate transitions. A rising edge on PWM initiates the turn-off of

the lower MOSFET (see “TIMING DIAGRAM” on page 8). After

Specifications” table on page 6. Adaptive shoot-through

circuitry monitors the PHASE voltage and determines the upper

upper MOSFETs from conducting simultaneously. Once this

delay period is complete, the upper gate drive begins to rise

A falling transition on PWM results in the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

PHASE voltage and the UGATE voltage are monitored, and

the lower gate is allowed to rise after PHASE drops below a

level or the voltage of UGATE to PHASE reaches a level

depending upon the current direction (See the following

the lower MOSFET.

Advanced Adaptive Zero Shoot-Through Deadtime

Control (Patent Pending)

These drivers incorporate a unique adaptive deadtime control

technique to minimize deadtime, resulting in high efficiency

from the reduced freewheeling time of the lower MOSFETs’

body-diode conduction, and to prevent the upper and lower

MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other has

turned off.

During turn-off of the lower MOSFET, the PHASE voltage is

monitored until it reaches a -0.2V/+0.8V trip point for a

forward/reverse current, at which time the UGATE is released

to rise. An auto-zero comparator is used to correct the

period. In the case of zero current, the UGATE is released

after 35ns delay of the LGATE dropping below 0.5V. During

the phase detection, the disturbance of LGATE’s falling

transition on the PHASE node is blanked out to prevent falsely

tripping. Once the PHASE is high, the advanced adaptive

shoot-through circuitry monitors the PHASE and UGATE

voltages during a PWM falling edge and the subsequent

UGATE turn-off. If either the UGATE falls to less than 1.75V

above the PHASE or the PHASE falls to less than +0.8V, the

LGATE is released to turn on.

Three-State PWM Input

A unique feature of these drivers and other Intersil drivers is

the addition of a shutdown window to the PWM input. If the

PWM signal enters and remains within the shutdown window

for a set holdoff time, the driver outputs are disabled and

both MOSFET gates are pulled and held low. The shutdown

state is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the “Electrical Specifications” table on

PWM

UGATE

LGATE

1.5V<PWM<3.2V

1.0V<PWM<2.6V

FIGURE 1. TIMING DIAGRAM

ISL6614A