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LMD18200 Datasheet(PDF) 9 Page - Texas Instruments |
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LMD18200 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 20 page LMD18200 www.ti.com SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 APPLICATION INFORMATION TYPES OF PWM SIGNALS The LMD18200 readily interfaces with different forms of PWM signals. Use of the part with two of the more popular forms of PWM is described in the following paragraphs. Simple, locked anti-phase PWM consists of a single, variable duty-cycle signal in which is encoded both direction and amplitude information (see Figure 11). A 50% duty-cycle PWM signal represents zero drive, since the net value of voltage (integrated over one period) delivered to the load is zero. For the LMD18200, the PWM signal drives the direction input (pin 3) and the PWM input (pin 5) is tied to logic high. Figure 11. Locked Anti-Phase PWM Control Sign/magnitude PWM consists of separate direction (sign) and amplitude (magnitude) signals (see Figure 12). The (absolute) magnitude signal is duty-cycle modulated, and the absence of a pulse signal (a continuous logic low level) represents zero drive. Current delivered to the load is proportional to pulse width. For the LMD18200, the DIRECTION input (pin 3) is driven by the sign signal and the PWM input (pin 5) is driven by the magnitude signal. Figure 12. Sign/Magnitude PWM Control SIGNAL TRANSITION REQUIREMENTS To ensure proper internal logic performance, it is good practice to avoid aligning the falling and rising edges of input signals. A delay of at least 1 µsec should be incorporated between transitions of the Direction, Brake, and/or PWM input signals. A conservative approach is be sure there is at least 500ns delay between the end of the first transition and the beginning of the second transition. See Figure 13. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LMD18200 |
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