3

FN6651.1

July 30, 2008

XSD BUS TIMING CHARACTERISTICS (Refer to XSD Bus Symbol Timing Definitions Tables beginning on page 8)

Programming Bit Rate

x = 0.5 to 4

2.89

-

23.12

kHz

XSD Input De-glitch Time

Pulse width narrower than the de-glitch time will not

cause the device to wake up

7-

20

µs

Device Wake-up Time

From falling-edge of break command issued by host to

falling-edge of break command returned by device

130

160

200

µs

Device Sleep Wait Time

From when the ‘11’ Opcode is detected to the shut-off

of the internal regulator

4-

-

µs

Auto-Sleep Time-out Period

From the last transition detected on the XSD bus to the

device going into sleep mode

-1

-

s

OTP ROM Write Time

From the last BT of the 2nd write data frame to when

device is ready to accept the next instruction

-1.8

1.9

ms

Hash Calculation Time

From the last BT of the Challenge Code Word from the

host to the Authentication Code being available for

read

-1

-

BT

Soft-Reset Time

From the last BT of the Soft-Reset instruction issued

by the host to the falling-edge of break command

returned by device

--

30

µs

Electrical Specifications

Unless otherwise noted, all parameters are established over the operational supply voltage and temperature

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Pin Descriptions

SOT-23

PIN NUMBER

TDFN

PIN NUMBER

PIN NAME

DESCRIPTION

1

1

VSS

System ground.

2

2, 3, 6, 7

NC

No connection.

3

4

VDD

Supply voltage.

4

5

TIO

Production test I/O pin. Used only during production testing. Must be left floating during

normal operation.

5

8

XSD

Communication bus with weak internal pull-down to VSS. This pin is a Schmitt-trigger input

and an open-drain output. An appropriate pull-up resistor is required on the host side.

ISL9206A