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D2-71083-LR Datasheet(PDF) 9 Page - Intersil Corporation |
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D2-71083-LR Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 33 page  D2-7xx83 9 FN7838.2 September 29, 2011 Two-Wire (I2C) Interface Port Timing (Figure 2) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages referenced to ground. SYMBOL DESCRIPTION MIN (Note 10) TYPICAL MAX (Note 10) UNIT fSCL SCL Frequency 100 kHz tbuf Bus Free Time Between Transmissions 4.7 µs twlowSCLx SCL Clock Low 4.7 µs twhighSCLx SCL Clock High 4.0 µs tsSTA Setup Time For a (Repeated) Start 4.7 µs thSTA Start Condition Hold Time 4.0 µs thSDAx SDA Hold From SCL Falling (Note 12) 1 µs tsSDAx SDA Setup Time to SCL Rising 250 ns tdSDAx SDA Output Delay Time From SCL Falling (Note 13) 3.5 µs tr Rise Time of Both SDA and SCL (Note 13) 1 µs tf Fall Time of Both SDA and SCL (Note 13) 300 ns tsSTO Setup Time For a Stop Condition 4.7 µs NOTE: 12. Data is clocked in as valid on next XTALI rising edge after SCL goes low. 13. Limits established by characterization and not production tested. FIGURE 2. I2C INTERFACE TIMING twhighSCLx twlowSCLx SCLx tsSTA SDAx (INPUT) SDAx (OUTPUT) thSDAx tsSDAx tBUF tsSTO tF tR thSTAx tdSDAx |
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