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MX26L1620TC-12 Datasheet(PDF) 10 Page - Macronix International

Part # MX26L1620TC-12
Description  16M-BIT [1M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
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Manufacturer  MCNIX [Macronix International]
Direct Link  http://www.macronix.com
Logo MCNIX - Macronix International

MX26L1620TC-12 Datasheet(HTML) 10 Page - Macronix International

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10
P/N:PM0827
REV. 0.4, JAN. 31, 2002
MX26L1620
First Bus
Second Bus Third Bus
Fourth Bus
Fifth Bus
Sixth Bus
Command
Bus
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Addr
Data
Addr
Data Addr
Data Addr
Data
Addr
Data Addr Data
Read(Note 5)
1
RA
RD
Reset(Note 6)
1
XXX
F0
Autoselect(Note 7)
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
C2
Device ID
4
555
AA
2AA
55
555
90
X01
22FE
Secured Sector
4
555
AA
2AA
55
555
90
x03
see
Factory Protect
Note9
Enter Secured Silicon
3
555
AA
2AA
55
555
88
Sector
Exit Secured Silicon
4
555
AA
2AA
55
555
90
xxx
00
Sector
Porgram
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Deep power down
3
555
AA
2AA
55
555
C0
SOFTWARE COMMAND DEFINTIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mode. Table 4 defines the valid register command
sequences. Either of the two reset command sequences
will reset the device(when applicable).
TABLE4. MX26L1620 COMMAND DEFINITIONS
Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE or
CE pulse.
PD=Data to be programmed at location PA. Data is
latched on the rising edge of WE or CE pulse.
All addresses are latched on the falling edge of WE or
CE, whichever happens later. All data are latched on ris-
ing edge of WE or CE, whichever happens first.
Notes:
1.See Table 1 for descriptions of bus operations.
2.All values are in hexadecimal.
3.Except when reading array or autoselect data, all bus cycles are write operation.
4.Address bits are don't care for unlock and command cycles, except when PA is required.
5.No unlock or command cycles required when device is in read mode.
6.The Reset command is required to return to the read mode when the device is in the autoselect mode or if Q5 goes
high.
7.The fourth cycle of the autoselect command sequence is a read cycle.
8.Command is valid when device is ready to read array data or when device is in autoselect mode.
9.The data is 88h for factory locked and 08h for non-factory locked.


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