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MX26L6420MC-12 Datasheet(PDF) 5 Page - Macronix International |
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MX26L6420MC-12 Datasheet(HTML) 5 Page - Macronix International |
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5 / 39 page  5 P/N:PM0823 REV. 0.5, JAN. 29, 2002 MX26L6420 AUTOMATIC PROGRAMMING The MX26L6420 is word programmable using the Auto- matic Programming algorithm. The Automatic Program- ming algorithm makes the external system do not need to have time out sequence nor to verify the data pro- grammed. The typical chip programming time at room temperature of the MX26L6420 is less than 150 sec- onds. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 un- lock write cycle and A0H) and a program command (pro- gram data and address). The device automatically times the programming pulse width, provides the program veri- fication, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling be- tween consecutive read cycles, provide feedback to the user as to the status of the programming operation. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 50 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 90 seconds. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using stand- ard microprocessor write timings. The device will auto- matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. During write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. All address are latched on the falling edge of WE or CE, whichever happens later. All data are latched on rising edge of WE or CE, which- ever happens first. MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, relia- bility, and cost effectiveness. The MX26L6420 electri- cally erases all bits simultaneously using Fowler-Nord- heim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injec- tion. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. After the state machine has completed its task, it will allow the command regis- ter to respond to its full command set. |
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