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BUK9628-100A Datasheet(PDF) 2 Page - NXP Semiconductors |
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BUK9628-100A Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 13 page BUK9628-100A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 02 — 26 April 2011 2 of 13 NXP Semiconductors BUK9628-100A N-channel TrenchMOS logic level FET 2. Pinning information 3. Ordering information 4. Limiting values Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 G gate SOT404 (D2PAK) 2 D drain 3S source mb D mounting base; connected to drain mb 13 2 S D G mbb076 Table 3. Ordering information Type number Package Name Description Version BUK9628-100A D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) SOT404 Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V VDGR drain-gate voltage RGS =20kΩ - 100 V VGS gate-source voltage -10 10 V ID drain current Tmb =25°C - 49 A Tmb = 100 °C - 34 A IDM peak drain current Tmb = 25 °C; pulsed - 195 A Ptot total power dissipation Tmb = 25 °C - 166 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C VGSM peak gate-source voltage pulsed; tp ≤ 50 µs -15 15 V Source-drain diode IS source current Tmb =25°C - 49 A ISM peak source current pulsed; Tmb = 25 °C - 195 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID =30A; Vsup ≤ 25 V; RGS =50 Ω; VGS =5 V; Tj(init) = 25 °C; unclamped -45 mJ |
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