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MX29F001TQC-90 Datasheet(PDF) 10 Page - Macronix International |
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MX29F001TQC-90 Datasheet(HTML) 10 Page - Macronix International |
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10 / 42 page  10 REV. 2.6, DEC. 29, 2003 P/N: PM0515 MX29F001T/B ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. SET-UP AUTOMATIC PROGRAM COMMANDS To initiate Automatic Program mode, A three-cycle com- mand sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Pro- gram command A0H. Once the Automatic Program command is initiated, the next WE pulse causes a transition to an active program- ming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE pulse. The rising edge of WE also begins the programming operation. The system does not require to provide further controls or timings. The device will auto- matically provide an adequate internally generated pro- gram pulse and verify margin. If the program operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode (no program verify command is required). WRITE OPERATION STATUS TOGGLE BIT-Q6 The MX29F001T/B features a "Toggle Bit" as a method to indicate to the host system that the Auto Program/ Erase algorithms are either in progress or complete. While the Automatic Program or Erase algorithm is in progress, successive attempts to read data from the device will result in Q6 toggling between one and zero. Once the Automatic Program or Erase algorithm is com- pleted, Q6 will stop toggling and valid data will be read. The toggle bit is valid after the rising edge of the sixth WE pulse of the six write pulse sequences for chip/sec- tor erase. The Toggle Bit feature is active during Automatic Pro- gram/Erase algorithms or sector erase time-out. (see section Q3 Sector Erase Timer) DATA POLLING-Q7 The MX29F001T/B also features Data Polling as a method to indicate to the host system that the Auto- matic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in opera- tion, an attempt to read the device will produce the comple- ment data of the data last written to Q7. Upon comple- tion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after the rising edge of the fourth WE pulse of the four write pulse sequences for automatic program. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data Polling feature is valid after the rising edge of the sixth WE pulse of six write pulse sequences for automatic chip/sector erase. The Data Polling feature is active during Automatic Pro- gram/Erase algorithm or sector erase time-out.(see sec- tion Q3 Sector Erase Timer) |
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