3

REV. 2.0, AUG. 27, 2003

P/N: PM0708

MX27C2000A

is the output control and should be used to gate data to

the output pins, independent of device selection.

Assuming that addresses are stable, address access

time (tACC) is equal to the delay from CE to output (tCE).

Data is available at the outputs tOE after the falling edge

of OE, assuming that CE has been LOW and addresses

have been stable for at least tACC - tOE.

STANDBY MODE

The MX27C2000A has a CMOS standby mode which

reduces the maximum VCC current to 100 uA. It is

placed in CMOS standby when CE is at VCC ±0.3 V. The

MX27C2000A also has a TTL-standby mode which

reduces the maximum VCC current to 1.5 mA. It is

placed in TTL-standby when CE is at VIH. When in

standby mode, the outputs are in a high-impedance

state, independent of the OE input.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two-

line control function is provided to allow for:

1. Low memory power dissipation,

2. Assurance that output bus contention will not

occur.

It is recommended that CE be decoded and used as the

primary device-selecting function, while OE be made a

common connection to all devices in the array and

connected to the READ line from the system control bus.

This assures that all deselected memory devices are in

their low-power standby mode and that the output pins

are only active when data is desired from a particular

memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby

conditions, transient current peaks are produced on the

rising and falling edges of Chip Enable. The magnitude

of these transient current peaks is dependent on the

output capacitance loading of the device. At a minimum,

a 0.1 uF ceramic capacitor (high frequency, low inherent

inductance) should be used on each device between Vcc

and GND to minimize transient effects. In addition, to

overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on EPROM

arrays, a 4.7 uF bulk electrolytic capacitor should be

used between VCC and GND for each eight devices. The

location of the capacitor should be close to where the

power supply is connected to the array.

NOTES:

1.VH = 12.0 V ± 0.5 V

2.X = Either VIH or VIL

3.A1 - A8 = A10 - A17 = VIL(For auto select)

4.See DC Programming Characteristics for VPP voltage during programming.

MODE SELECT TABLE

PINS

MODE

CE

OE

PGM

A0

A9

VPP

OUTPUTS

Read

VIL

VIL

X

X

X

VCC

DOUT

Output Disable

VIL

VIH

X

X

X

VCC

High Z

Standby (TTL)

VIH

X

X

X

X

VCC

High Z

Standby (CMOS)

VCC±0.3V

X

X

X

X

VCC

High Z

Program

VIL

VIH

VIL

X

X

VPP

DIN

Program Verify

VIL

VIL

VIH

X

X

VPP

DOUT

Program Inhibit

VIH

X

X

X

X

VPP

High Z

Manufacturer Code(3)

VIL

VIL

X

VIL

VH

VCC

C2H

Device Code(3)

VIL

VIL

X

VIH

VH

VCC

C3H