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MX29F800TMC-70 Datasheet(PDF) 8 Page - Macronix International |
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MX29F800TMC-70 Datasheet(HTML) 8 Page - Macronix International |
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8 / 42 page  8 P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 READ/RESET COMMAND The read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the com- mand register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com- mand must then be written to place the device in the desired state. SILICON-ID-READ COMMAND Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM pro- grammers typically access signature codes by raising A9 to a high voltage(VID). However, multiplexing high voltage onto address lines is not generally desired sys- tem design practice. The MX29F800T/B contains a Silicon-ID-Read opera- tion to supplement traditional PROM programming meth- odology. The operation is initiated by writing the read silicon ID command sequence into the command reg- ister. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of D6H/22D6H for MX29F800T, 58H/2258H for MX29F800B. SET-UP AUTOMATIC CHIP/SECTOR ERASE Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex) Manufacture code Word VIL VIL 00H 1 1 0 0 0 0 1 0 00C2H Byte VIL VIL X 1 1 0 0 0 0 1 0 C2H Device code Word VIH VIL 22H 1 1 0 1 0 1 1 0 22D6H for MX29F800T Byte VIH VIL X 1 1 0 1 0 1 1 0 D6H Device code Word VIH VIL 22H 0 1 0 1 1 0 0 0 2258H for MX29F800B Byte VIH VIL X 0 1 0 1 1 0 0 0 58H Sector Protection X VIH X 0 0 0 0 0 0 0 1 01H (Protected) Verification X VIH X 0 0 0 0 0 0 0 0 00H (Unprotected) TABLE 3. EXPANDED SILICON ID CODE COMMANDS Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cy- cles are then followed by the chip erase command 10H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify be- gin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the erase operation exceed internal timing limit. The automatic erase begins on the rising edge of the last WE or CE, whichever happens first pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two con- secutive read cycles, at which time the device returns to the Read mode. |
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