NUP1301U

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 1 — 28 January 2011

8 of 14

NXP Semiconductors

NUP1301U

Ultra low capacitance ESD protection array

8.

Application information

Protection of a single (high-speed) data line in rail-to-rail configuration. The protected data

line is connected to pin 3. Pin 1 is connected to ground (GND) and pin 2 is connected to

voltage drop of one diode, the transient is directed either to the supply rail or to GND.

The advantages of these solutions are: low line capacitance (0.6 pF typically), fast

response time, and low clamping voltage.

Circuit board layout and protection device placement:

Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)

and surge transients. The following guidelines are recommended:

1. Place the NUP1301U as close to the input terminal or connector as possible.

2. The path length between the NUP1301U and the protected line should be minimized.

3. Keep parallel signal paths to a minimum.

4. Avoid running protected conductors in parallel with unprotected conductors.

5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and

ground loops.

6. Minimize the length of the transient return path to ground.

7. Avoid using shared transient return paths to a common ground point.

8. Ground planes should be used whenever possible. For multilayer PCBs, use ground

vias.

9.

Test information

9.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is

suitable for use in automotive applications.

Fig 8.

Typical application for the protection of one signal line

006aac518

Audio

interface

D2

NUP1301U

D1

NUP1301U