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MX29LV401BXBI-90 Datasheet(PDF) 9 Page - Macronix International |
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MX29LV401BXBI-90 Datasheet(HTML) 9 Page - Macronix International |
9 / 56 page 9 P/N:PM0853 MX29LV401T/B REV. 0.0, SEP. 14, 2001 REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory contect occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs.The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory , the sysytem must drive WE and CE to VIL, and OE to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The "byte Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors , or the entire device. Table indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data."section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal reqister (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODE When using both pins of CE and RESET, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. IF CE and RESET are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby currect will be larger. During Auto Algorithm operation, Vcc active current (Icc2) is required even CE = "H" until the operation is complated. The de- vice can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data. OUTPUT DISABLE With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. RESET OPERATION The RESET pin provides a hardware method of resetting the device to reading array data. When the RESET pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET pluse. The device also resets the internal state machine to reading array data.The operation that was interrupted should be reinitated once the device is ready to accept another command sequence, to ensure data integrity Current is reduced for the duration of the RESET pulse. When RESET is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS±0.3V, the standby current will be greater. The RESET pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firm-ware from |
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