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KAD5510P-12Q48 Datasheet(PDF) 3 Page - Intersil Corporation

Part # KAD5510P-12Q48
Description  Low Power 10-Bit, 250/210/170/125MSPS ADC
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

KAD5510P-12Q48 Datasheet(HTML) 3 Page - Intersil Corporation

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KAD5510P
3
FN7693.2
May 2, 2011
Pin Descriptions - 48 Ld QFN
PIN NUMBER
LVDS [LVCMOS] NAME
LVDS [LVCMOS] FUNCTION
1, 9, 13, 17, 47
AVDD
1.8V Analog Supply
2, 3, 4, 11, 21, 22,
23, 24
DNC
Do Not Connect
5, 8, 12, 48
AVSS
Analog Ground
6, 7
VINN, VINP
Analog Input Negative, Positive
10
VCM
Common Mode Output
14, 15
CLKP, CLKN
Clock Input True, Complement
16
NAPSLP
Tri-Level Power Control (Nap, Sleep modes)
18
RESETN
Power On Reset (Active Low, see page 16)
19, 29, 42
OVSS
Output Ground
20, 37
OVDD
1.8V Output Supply
25
D0N
[NC]
LVDS DDR Logical Bits 1, 0 Output Complement
[NC in LVCMOS]
26
D0P
[D0]
LVDS DDR Logical Bits 1, 0 Output True
[CMOS DDR Logical Bits 1, 0 in LVCMOS]
27
D1N
[NC]
LVDS DDR Logical Bits 3, 2 Output Complement
[NC in LVCMOS]
28
D1P
[D1]
LVDS DDR Logical Bits 3, 2 Output True
[CMOS DDR Logical Bits 3, 2 in LVCMOS]
30
RLVDS
LVDS Bias Resistor (Connect to OVSS with a 10k
Ω, 1% resistor)
31
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
32
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
33
D2N
[NC]
LVDS DDR Logical Bits 5, 4 Output Complement
[NC in LVCMOS]
34
D2P
[D2]
LVDS DDR Logical Bits 5, 4 Output True
[CMOS DDR Logical Bits 5, 4 in LVCMOS]
35
D3N
[NC]
LVDS DDR Logical Bits 7, 6 Output Complement
[NC in LVCMOS]
36
D3P
[D3]
LVDS DDR Logical Bits 7, 6 Output True
[CMOS DDR Logical Bits 7, 6 in LVCMOS]
38
D4N
[NC]
LVDS DDR Logical Bits 9, 8 Output Complement
[NC in LVCMOS]
39
D4P
[D4]
LVDS DDR Logical Bits 9, 8 Output True
[CMOS DDR Logical Bits 9, 8 in LVCMOS]
40
ORN
[NC]
LVDS Over Range Complement
[NC in LVCMOS]
41
ORP
[OR]
LVDS Over Range True
[LVCMOS Over Range]
43
SDO
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
44
CSB
SPI Chip Select (active low)
45
SCLK
SPI Clock
46
SDIO
SPI Serial Data Input/Output
PAD
(Exposed Paddle)
AVSS
Analog Ground (Connect to a low thermal impedance analog ground plane with
multiple vias)
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection).


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