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KAD5514P-17Q48 Datasheet(PDF) 3 Page - Intersil Corporation |
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KAD5514P-17Q48 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 34 page 3 FN6804.2 September 10, 2009 Table of Contents Pin-Compatible Family...................................................... 1 Key Specifications ............................................................ 1 Electrical Specifications ....................................................4 Digital Specifications ........................................................ 6 Timing Diagrams ............................................................... 7 Switching Specifications .................................................. 8 Pinout/Package Information............................................. 9 Pin Descriptions - 72QFN ................................................ 9 Pin Descriptions - 48QFN .............................................. 12 Typical Performance Curves ...........................................14 Theory of Operation ........................................................ 17 Functional Description ................................................... 17 Power-On Calibration .................................................... 17 User-Initiated Reset ....................................................... 18 Analog Input .................................................................. 19 Clock Input..................................................................... 19 Jitter ............................................................................... 20 Voltage Reference ......................................................... 20 Digital Outputs ............................................................... 20 Over-Range Indicator .................................................... 20 Power Dissipation .......................................................... 20 Nap/Sleep ...................................................................... 21 Data Format................................................................... 21 Serial Peripheral Interface ............................................. 22 SPI Physical Interface ................................................... 23 SPI Configuration .......................................................... 24 Device Information ........................................................ 24 Indexed Device Configuration/Control .......................... 24 Global Device Configuration/Control ............................. 25 Device Test ................................................................... 26 SPI Memory Map .......................................................... 27 Equivalent Circuits ......................................................... 29 72 Pin/48 Pin Package Options ..................................... 30 ADC Evaluation Platform ............................................... 30 Layout Considerations ................................................... 30 Split Ground and Power Planes .................................... 30 Clock Input Considerations ........................................... 30 Exposed Paddle ............................................................ 30 Bypass and Filtering...................................................... 30 LVDS Outputs ............................................................... 30 LVCMOS Outputs ......................................................... 30 Unused Inputs ............................................................... 30 Definitions.................................................................... 31 Revision History ............................................................. 32 Package Outline Drawing ................................................. 34 KAD5514P |
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