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KAD5514P-12Q48 Datasheet(PDF) 7 Page - Intersil Corporation |
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KAD5514P-12Q48 Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 34 page  7 FN6804.2 September 10, 2009 Timing Diagrams FIGURE 1A. DDR FIGURE 1B. SDR FIGURE 1. LVDS TIMING DIAGRAMS (See “Digital Outputs” on page 20) FIGURE 2A. DDR FIGURE 2B. SDR FIGURE 2. CMOS TIMING DIAGRAM (See “Digital Outputs” on page 20) LATENCY = L CYCLES tDC tPD tA SAMPLE N tCPD INP INN CLKN CLKP CLKOUTN CLKOUTP ODD BITS N-L N-L ODD BITS ODD BITS EVEN BITS N-L + 1 N-L + 1 N-L + 2 N-L + 2 EVEN BITS EVEN BITS EVEN BITS D[12/10/8/6/4/2/0]P D[12/10/8/6/4/2/0]N N LATENCY = L CYCLES tDC tPD tA SAMPLE N tCPD INP INN CLKN CLKP CLKOUTN CLKOUTP DATA DATA N-L + 1 D[13/0]P D[13/0]N N DATA N-L SAMPLE N tDC tPD tA INP INN CLKN CLKOUT CLKP D[12/10/8/6/4/2/0] LATENCY = L CYCLES ODD BITS N-L N-L ODD BITS ODD BITS EVEN BITS N-L + 1 N-L + 1 N-L + 2 N-L + 2 EVEN BITS EVEN BITS EVEN BITS N tCPD SAMPLE N INP INN CLKN CLKOUT CLKP tCPD tA D[13/0] tDC tPD DATA N-L DATA DATA N-L + 1 N LATENCY = L CYCLES KAD5514P |
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