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SY100S322JC Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100S322JC Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 5 page s Max. propagation delay of 700ps s IEE min. of –55mA s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75K Ω input pull-down resistors s 70% faster than Fairchild 300K at lower power s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages FEATURES DESCRIPTION The SY100S322 is an ultra-fast buffer designed for use in high-performance ECL systems. The device provides nine non-inverting buffers with single-ended outputs. The inputs on the device have 75K Ω pull-down resistors. SY100S322 9-BIT BUFFER BLOCK DIAGRAM PIN CONFIGURATIONS D1 O2 O1 D2 D3 O4 O3 D4 D5 O6 O5 D6 D7 O8 O7 D8 D9 O9 D5 D4 VCCA O4 O6 O5 D1 D3 O3 D2 O2 VCCA 18 17 16 15 14 13 1 2 3 4 5 6 7 24 8 23 9 22 10 21 11 20 12 19 Top View Flatpack F24-1 O7 O8 VCCA VCC O9 VCC D6 VEE VCCA D7 D8 VEES 4 3 2 1 28 27 12 13 14 15 16 17 19 11 20 10 21 9 22 8 23 7 24 6 Top View PLCC J28-1 O1 D9 26 18 25 5 Rev.: G Amendment: /0 Issue Date: July, 1999 Pin Function D1 – D9 Data Inputs O1 – O9 Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs PIN NAMES 1 |
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