6

SY10E136

SY100E136

Micrel

count status for the next occurrence of terminal count on

the LSC. This ripple propagation will not affect the count

without affecting the count operation of the chain.

The only limiting factor which could reduce the count

frequency of the chain as compared to a free running single

Programmable Divider

be configured as a programmable divider. Figure 3 illustrates

the configuration for a 6-bit count-down programmable

divider. If for some reason a count-up divider is preferred,

Examination of the truth table for the E136 shows that when

count-down mode and will count towards an all zero state

upon successive clock pulses.

Knowing this and the

build programmable dividers.

For a programmable divider, one must to load a

predesignated number into the counter and count to terminal

count. Upon terminal count, the counter should automatically

reload the divide number. With the architecture shown in

Figure 3, when the counter reaches terminal count, the

This,

longer at terminal count, thereby placing the counter back

into the count mode.

CLK

ACTIVE

LOW

DQ

Figure 2. Look-Ahead-Carry Input Structure

Note from the waveforms that the look-ahead-carry output

clock period.

The input structure for look-ahead-carry-in

be enabled to count (either count up or count down). The

order E136 and, therefore, are only asserted for a single

If the counter previous to a given counter is at terminal

counter will be in the "LOW" state. This signals the given

counter that it will need to count one upon the next terminal

count of the least significant counter (LSC).

output of the LSC will pulse low one clock period before it

are in the LOW state, the next clock pulse will cause the

least significant counter to roll over and all higher order

During the clock pulse in which the higher order counter

order counter will ripple through the chain to update the

CLK

CLOCK

"LO"

Figure 3. 6-bit Programmable Divider

Divide

Preset Data Inputs

Ratio

D5

D4

D3

D2

D1

D0

2L

L

L

L

L

H

3L

L

L

L

H

L

4L

L

L

L

H

H

5L

L

L

H

L

L

**

*

*

*

*

*

**

*

*

*

*

*

36

H

L

L

L

H

H

37

H

L

L

H

L

L

38

H

L

L

H

L

H

**

*

*

*

*

*

**

*

*

*

*

*

62

HH

HH

L

H

63

HH

HH

H

L

64

HH

HH

H

H

Table 1. Preset Inputs Versus Divide Ratio