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SY10E150JCTR Datasheet(PDF) 1 Page - Micrel Semiconductor

Part # SY10E150JCTR
Description  6-BIT D LATCH
Download  4 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY10E150JCTR Datasheet(HTML) 1 Page - Micrel Semiconductor

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s 700ps max. propagation delay
s Extended 100E VEE range of –4.2V to –5.5V
s Differential outputs
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75K
Ω input pulldown resistors
s Fully compatible with Motorola MC10E/100E150
s Available in 28-pin PLCC package
FEATURES
6-BIT D
LATCH
The SY10/100E150 are 6-bit D latches with differential
outputs designed for use in new, high- performance ECL
systems. When both Latch Enables (LEN1, LEN2) are at a
logic LOW, the latch is in the transparent mode and input
data propagates through to the output. A logic HIGH on
either LEN1 or LEN2 (or both) latches the input data. The
Master Reset (MR) overrides all other signals to set the Q
outputs to a logic LOW.
DESCRIPTION
SY10E150
SY100E150
Rev.: D
Amendment: /0
Issue Date: November, 1998
BLOCK DIAGRAM
Pin
Function
D0–D5
Data Inputs
LEN1, LEN2
Latch Enables
MR
Master Reset
Q0–Q5
True Outputs
Q0–Q5
Inverting Outputs
VCCO
VCC to Output
PIN NAMES
PIN CONFIGURATION
D
R
D
R
D
R
D
R
D
R
D
R
MR
D0
LEN1
LEN2
D1
D2
D3
D4
D5
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
VEE
D5
D4
D1
D2
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
56789
10 11
D0
D3
Q4
PLCC
TOP VIEW
J28-1
Q4
VCC
Q3
Q3
Q2
Q2
1


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