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X9221AUP Datasheet(PDF) 3 Page - Intersil Corporation |
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X9221AUP Datasheet(HTML) 3 Page - Intersil Corporation |
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3 / 15 page  1 0 0 A3 A2 A1 A0 Device Type Identifier Device Address 1 3 FN8163.2 August 30, 2006 PIN NAMES PRINCIPLES OF OPERATION The X9221A is a highly integrated microcircuit incor- porating two resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9221A supports a bidirectional bus oriented pro- tocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and pro- vide the clock for both transmit and receive operations. Therefore, the X9221A will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9221A are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9221A continu- ously monitors the SDA and SCL lines for the start condition, and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop con- dition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. See Figure 7. The X9221A will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the com- mand byte. If the command is followed by a data byte the X9221A will respond with a final acknowledge. Array Description The X9221A is comprised of two resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a FET switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six least significant bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the WCR. These data registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most signifi- cant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9221A this is fixed as 0101[B]. Figure 1. Slave Address Symbol Description SCL Serial Clock SDA Serial Data A0–A3 Address VH0/RH0-VH1/RH1, VL0/RH0-VL1/RL0 Potentiometers (terminal equivalent) VW0/RW0-VW1/RW1 Potentiometers (wiper equivalent) RES Reserved (Do not connect) X9221A |
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Similar Description - X9221AUP |
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