ZL6105

5

FN6906.5

December 19, 2013

Pin Configuration

ZL6105

(36 LD QFN)

TOP VIEW

27

26

25

24

23

22

21

1

2

3

4

5

6

7

DGND

SYNC

SA0

SA1

ILIM

CFG0

SCL

VDD

BST

GH

SW

PGND

GL

VR

8

9

20

19

ISENA

ISENB

SDA

SALRT

EXPOSED PADDLE*

*CONNECT TO SGND

Pin Descriptions

PIN

LABEL

TYPE (Note 1)

DESCRIPTION

1

DGND

PWR

Digital ground. Common return for digital signals. Connect to low impedance ground plane.

2

SYNC

I/O,M (Note 2)

Clock synchronization input. Used to set switching frequency of internal clock or for synchronization to

external frequency reference.

3

SA0

I, M

Serial address select pins. Used to assign unique SMBus address to each IC or to enable certain

management features.

4SA1

5

ILIM

I, M

Current limit select. Sets the overcurrent threshold voltage for ISENA and ISENB.

6

CFG0

I, M

Configuration pin. Used to setup current sharing and non-linear response.

7

SCL

I/O

Serial clock. Connect to external host and/or to other ZL devices.

8

SDA

I/O

Serial data. Connect to external host and/or to other ZL devices.

9

SALRT

O

Serial alert. Connect to external host if desired.

10

FC0

I

Loop compensation configuration pins.

11

FC1

12

V0

I

13

V1

14

UVLO

I, M

15

SS

I, M

Soft start pin. Sets the output voltage ramp time during turn-on and turn-off. Sets the delay from when EN

is asserted until the output voltage starts to ramp.

16

VTRK

I

Tracking sense input. Used to track an external voltage source.

17

VSEN+

I

Output voltage feedback. Connect to output regulation point.

18

VSEN-

I

Output voltage feedback. Connect to load return or ground regulation point.

19

ISENB

I

Differential voltage input for current limit.