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SY10E167JCTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY10E167JCTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 3 page 5-127 SY10E167 SY100E167 SYNERGY SEMICONDUCTOR © 1999 Micrel-Synergy s 1000MHz min. operating frequency s Extended 100E VEE range of –4.2V to –5.5V s 800ps max. clock to output s Single-ended outputs s Asynchronous Master Reset s Dual clocks s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K Ω input pulldown resistors s ESD protection of 2000V s Fully compatible with Motorola MC10E/100E167 s Available in 28-pin PLCC package FEATURES The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. The Select (SEL) control allows one of the two data inputs to the multiplexer to pass through. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as control for the six flip-flops. The selected data are transferred to the flip-flops on the rising edge of CLK1 or CLK2 (or both). The multiplexer operation is controlled by the Select (SEL) signal which selects one of the two bits of input data at each mux to be passed through. When a logic HIGH is applied to the Master Reset (MR) signal, it operates asychronously to take all outputs Q to a logic LOW. DESCRIPTION 6-BIT 2:1 MUX-REGISTER Rev.: C Amendment: /1 Issue Date: February, 1998 SY10E167 SY100E167 BLOCK DIAGRAM PIN NAMES Pin Function D0a–D5a Input Data a D0b–D5b Input Data b SEL Select Input CLK1, CLK2 Clock Inputs MR Master Reset Q0–Q5 Data Outputs VCCO VCC to Output PIN CONFIGURATION TOP VIEW PLCC J28-1 26 27 28 1 2 3 4 18 17 16 15 14 13 12 25 24 23 22 21 20 19 5 6 7 8 9 10 11 VEE D5b D0a MR CLK2 CLK1 SEL VCC Q5 Q4 Q1 Q3 Q2 VCCO D R Q MUX SEL D R Q D R Q D R Q D R Q D R Q0 Q1 Q2 Q3 Q4 Q5 Q MR D0a CLK1 CLK2 SEL D0b D1a D1b D2a D2b D3a D3b D4a D4b D5a D5b MUX SEL MUX SEL MUX SEL MUX SEL MUX SEL |
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