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SY10E167

SY100E167

SYNERGY

SEMICONDUCTOR

© 1999 Micrel-Synergy

s 1000MHz min. operating frequency

s 800ps max. clock to output

s Single-ended outputs

s Asynchronous Master Reset

s Dual clocks

s Fully compatible with industry standard 10KH,

100K ECL levels

s Internal 75K

s ESD protection of 2000V

s Fully compatible with Motorola MC10E/100E167

s Available in 28-pin PLCC package

FEATURES

The SY10/100E167 offer six 2:1 multiplexers followed

by D flip-flops with single-ended outputs, designed for use

in new, high-performance ECL systems. The Select (SEL)

control allows one of the two data inputs to the multiplexer

as control for the six flip-flops.

The selected data are

The multiplexer operation is controlled by the Select

(SEL) signal which selects one of the two bits of input data

at each mux to be passed through.

When a logic HIGH is applied to the Master Reset (MR)

signal, it operates asychronously to take all outputs Q to a

logic LOW.

DESCRIPTION

6-BIT 2:1 MUX-REGISTER

Rev.: C

Amendment: /1

Issue Date: February, 1998

SY10E167

SY100E167

BLOCK DIAGRAM

PIN NAMES

Pin

Function

Input Data a

Input Data b

SEL

Select Input

Clock Inputs

MR

Master Reset

Data Outputs

PIN CONFIGURATION

TOP VIEW

PLCC

J28-1

26

27

28

1

2

3

4

18

17

16

15

14

13

12

25 24 23 22 21 20 19

5

6

7

8

9

10 11

MR

SEL

D

R

Q

MUX

SEL

D

R

Q

D

R

Q

D

R

Q

D

R

Q

D

R

Q

MR

SEL

MUX

SEL

MUX

SEL

MUX

SEL

MUX

SEL

MUX

SEL