5

ClockWorks™

SY10E195

SY100E195

Micrel

APPLICATIONS INFORMATION

Cascading Multiple E195s

To increase the programmable range of the E195,

internal cascade circuitry has been included. This circuitry

allows for the cascading of multiple E195s without the

need for any external gating. Furthermore, this capability

requires only one more address line per added E195.

Obviously, cascading multiple PDCs will result in a larger

programmable range; however, this increase is at the

expense of a longer minimum delay.

Figure 1 illustrates the interconnect scheme for

cascading two E195s. As can be seen, this scheme can

of the E195 is the cascade control pin.

With the

signals the need for a larger programmable range than

is achievable with a single device.

An expansion of the latch section of the block diagram

is pictured below. Use of this diagram will simplify the

explanation of how the cascade circuitry works. When

be low, while the cascade bar output will be a logical

high. In this condition, the SET MIN pin of chip #2 will

be asserted and, thus, all of the latches of chip #2 will

be reset and the device will be set at its minimum delay.

Since the RESET and SET inputs of the latches are

not affect the operation of chip #2.

Chip #1, on the other hand, will have both SET MIN

and SET MAX de-asserted so that its delay will be

needed is greater than can be achieved with 31.75 gate

asserted to signal the need to cascade the delay to the

pin of chip #2 will be de-asserted and the delay will be

other hand, will have its SET MAX pin asserted, resulting

address bus.

will be set.

In addition, to maintain monotonicity, an

additional gate delay is selected in the cascade circuitry.

increases from 31.75 gates to 32 gates. A 32-gate delay

is the maximum delay setting for the E195.

To expand this cascading scheme to more devices,

outputs of the current most significant E195 to the new

most significant E195 in the same manner as pictured in

Figure 1. The only addition to the logic is the increase

of one line to the address bus for cascade control of the

second PDC.

Figure 1. Cascading Interconnect Architecture

E196

Chip #1

LEN

VEE

IN

VBB

IN

VCC

VCCO

Q

VCCO

Q

E196

Chip #2

LEN

VEE

IN

VBB

IN

VCC

VCCO

Q

VCCO

Q

ADDRESS BUS (A0 – A6)

Input

Output