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ELECTRICAL CHARACTERISTICS

TAS5261

SLES188 – AUGUST 2006

Audio frequency = 1 kHz, PVDD_x = 50 V, GVDDx = 12 V, VDD = 12 V, R

T

TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system

configuration are in accordance with recommended design guidelines.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Internal Voltage Regulator and Current Consumption

Voltage regulator,

VREG

3.3

V

only used as reference node

Operating, 50% duty cycle

7.7

VDD supply current

mA

Idle, reset mode

6.7

50% duty cycle

15

GVDD_x gate-supply current

mA

per half bridge

Idle, reset mode

1.5

50% duty cycle

23

mA

Half-bridge idle current

Reset mode (RESET = 1),

100

µA

No switching

Output-Stage MOSFETs

Drain-to-source resistance, low side

40

m

Ω

Drain-to-source resistance, high side

40

m

Ω

I/O Protection

Undervoltage protection limit, GVDD_x

8.5

V

OTW

Overtemperature warning

125

°C

OTW hysteresis

25

°C

OTE

Overtemperature error threshold

155

°C

OTE hysteresis

30

°C

OTE-OTW

Temperature delta between OTW and OTE

30

°C

differential

OLPC

Overload protection time constant

20

ms

Resistor programmable high end

15

16

17

A

with OC_ADJ = 22 k

Programming resistor

22

100

k

Ω

Connected when RESET is high to

Pulldown resistor at the output of each

provide a charge path for the

2.5

k

Ω

half-bridge

bootstrap capacitor

PWM

PWM Activity Detector

Lack of transition of any PWM input

13

µs

(1)

DC measurement with 1-ms pulse

9

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