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SY100E452JITR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100E452JITR Datasheet(HTML) 1 Page - Micrel Semiconductor |
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1 / 4 page  Pin Function D [0:4], /D [0:4] Differential Data Inputs MR Master Reset Input CLK, /CLK Differential Clock Input VBB VBB Reference Output Q [0:4], Q [0:4] Differential Data Outputs VCCO VCC to Output DESCRIPTION FEATURES s Differential D, CLK and Q s Extended 100E VEE range of –4.2V to –5.5V s VBB output for single-ended use s 1100MHz min. toggle frequency s Asynchronous Master Reset s Fully compatible with Motorola MC10E/100E452 s Available in 28-pin PLCC package The SY10/100E452 are 5-bit differential registers with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the devices. The clamping action will assert the /D and the /CLK sides of the inputs. Because of the edge-triggered flip-flop nature of the devices, simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. The fully differential design of the devices makes them ideal for very high frequency applications where a registered data path is necessary. 5-BIT DIFFERENTIAL REGISTER SY10E452 SY100E452 Rev.: D Amendment: /0 Issue Date: May, 1999 BLOCK DIAGRAM D0 D0 Q0 Q0 VBB CLK CLK D Q R MR D1 D1 Q1 Q1 D Q R D2 D2 Q2 Q2 D Q R D3 D3 Q3 Q3 D Q R D4 D4 Q4 Q4 D Q R PIN CONFIGURATION PIN NAMES 18 17 16 15 14 13 12 56 7 8 9 10 11 26 27 28 1 2 3 4 TOP VIEW PLCC J28-1 25 24 23 22 21 20 19 MR CLK VEE VBB D2 CLK D2 Q3 VCC Q2 Q1 Q3 Q2 Q1 1 |
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