The SY10/100EL34/L are low skew

÷2, ÷4, ÷8 clock

generation chips designed explicitly for low skew clock

generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

coupled into the device. If a single-ended input is to be

input and bypassed to ground via a 0.01

µF capacitor.

reference for the input of the EL34/L under single-ended

input conditions. As a result, this pin can only source/

sink up to 0.5mA of current.

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the divider stages. The

internal enable flip-flop is clocked on the falling edge of

the input clock, therefore, all associated specification

limits are referenced to the negative edge of the clock

input.

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple EL34/Ls in a system.

Pin

Function

CLK

Differential Clock Inputs

EN

Synchronous Enable

MR

Master Reset

Reference Output

Differential

÷2 Outputs

Differential

÷4 Outputs

Differential

÷8 Outputs

DESCRIPTION

PIN NAMES

FEATURES

Rev.: F

Amendment: /0

Issue Date:

August, 1998

5V/3.3V

GENERATION CHIP

ClockWorks™

SY10EL34/L

SY100EL34/L

PIN CONFIGURATION/BLOCK DIAGRAM

SOIC

TOP VIEW

s 3.3V and 5V power supply options

s 50ps output-to-output skew

s Synchronous enable/disable

s Master Reset for synchronization

s Internal 75K

s Available in 16-pin SOIC package

EN

NC

CLK

CLK

MR

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

R

Q

÷2

Q

R

÷4

Q

÷8

R

Q D

R

1