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SY100ELT21LZCTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100ELT21LZCTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 4 page Pin Function Q TTL Output D, /D Differential LVPECL Inputs V CC +3.3V Supply V BB Reference Output GND Ground DESCRIPTION s 3.3V power supply s 2.0ns typical propagation delay s Low power s Differential LVPECL inputs s 24mA TTL outputs s Flow-through pinouts s Available in 8-pin SOIC package The SY10/100ELT21L are single differential LVPECL- to-LVTTL translators using a single +3.3V power supply. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and low skew single gate design make the ELT21L ideal for applications that require the translation of a clock or data signal where minimal space, low power, and low cost are critical. V BB allows a differential, single-ended, or AC-coupled interface to the device. If used, the V BB output should be bypassed to V CC with 0.01µF capacitor. Under open input conditions, the /D will be biased at a V CC/2 voltage level and the D input will be pulled to ground. This condition will force the Q output low to provide added stability. The ELT21L is available in both ECL standards: the 10ELT is compatible with positive ECL 10H logic levels, while the 100ELT is compatible with positive ECL 100K logic levels. FEATURES 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR PIN NAMES PIN CONFIGURATION/BLOCK DIAGRAM ClockWorks™ SY10ELT21L SY100ELT21L 1 NC D D VBB 8VCC Q NC GND 7 6 5 2 3 4 PECL TTL 1 Rev.: B Amendment: /0 Issue Date: April 2000 |
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