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SY10H601JC Datasheet(PDF) 1 Page - Micrel Semiconductor

Part # SY10H601JC
Description  9-BIT ECL-TO-TTL WITH 3-STATE ENABLE
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY10H601JC Datasheet(HTML) 1 Page - Micrel Semiconductor

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Pin
Function
GND
TTL Ground (0V)
VCCE
ECL VCC (0V)
VCCT
TTL Supply (+5.0V)
VEE
ECL Supply (–5.2/–4.5V)
D0–D8
Data Inputs (ECL)
Q0–Q8
Data Outputs (TTL)
OEECL
3-State Control (ECL)
OETTL
3-State Control (TTL)
DESCRIPTION
FEATURES
s 9-bit ideal for byte-parity applications
s 3-state TTL outputs
s Flow-through configuration
s Extra TTL and ECL power/ground pins to minimize
switching noise
s ECL and TTL 3-state control inputs
s 4.8ns max. delay into 50pF, 9.6ns into 200pF (all
outputs switching)
s PNP TTL inputs for low loading
s Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s Fully compatible with Motorola MC10H/100H601
s Available in 28-pin PLCC package
The SY10/100H601 are 9-bit, dual supply ECL-to-TTL
translators. Devices in the Micrel-Synergy 9-bit translator
series utilize the 28-lead PLCC for optimal power pinning,
signal flow-through and electrical performance.
The devices feature a 48mA TTL output stage and AC
performance is specified into both a 50pF and 200pF
load capacitance. For the 3-state output disable, both
ECL and TTL control inputs are provided, allowing
maximum design flexibility.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
9-BIT ECL-TO-TTL
WITH 3-STATE ENABLE
SY10H601
SY100H601
Rev.: D
Amendment: /0
Issue Date: February, 1998
PIN NAMES
BLOCK DIAGRAM
PIN CONFIGURATION
18
17
16
15
14
13
12
56789
10 11
26
27
28
1
2
3
4
TOP VIEW
PLCC
25 24 23 22 21 20 19
Q4
Q3
VCCT
Q2
GND
Q1
Q0
D8
D7
VCCE
D6
D5
D4
D3
Q0
D0
ECL
TTL
OEECL
OETTL
Q1
D1
Q2
D2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
Q8
D8
1


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