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SY89429VJCTR Datasheet(PDF) 5 Page - Micrel Semiconductor |
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SY89429VJCTR Datasheet(HTML) 5 Page - Micrel Semiconductor |
5 / 9 page 5 ClockWorks™ SY89429V Micrel M,N S_CLOCK S_DATA S_LOAD P_LOAD M[8:0] N[1:0] T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 PROGRAMMING INTERFACE Programming the device is accomplished by properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can be represented by this formula: Where FXTAL is the crystal frequency, M is the loop divider modulus, and N is the output divider modulus. Note that it is possible to select values of M such that the PLL is unable to achieve loop lock. To avoid this, always make sure that M is selected to be 200 ≤ M ≤ 400 for a 16MHz input reference. M[8:0] and N[1:0] are normally specified once at power-on, through the parallel interface, and then possibly again through the serial interface. This approach allows the designer to bring up the application at one frequency and then change or fine- tune the clock, as the ability to control the serial interface becomes available. To minimize transients in the frequency domain, the output should be varied in the smallest step size possible. The TEST output provides visibility for one of several internal nodes (as determined by the T[1:0] bits in the serial configuration stream). It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the TTL output may not be able to toggle fast enough for some of the higher output frequencies. The T2, T1, T0 configuration latches are preset to 000 when P_LOAD is low, so that the FOUT outputs are as jitter-free as possible. The serial configuration port can be used to select one of the alternate functions for this pin. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M8). When T[2:0] is set to 100 the SY89429V is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree (See detailed Block Diagram). Because the S_CLOCK is a TTL level the input frequency is limited to 250MHz or less. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 125MHz as the minimum divide ratio of the N counter is 2. Note that the M counter output on the TEST output will not be a 50% duty cycle due to the way the divider is implemented. First Bit Last Bit T2 T1 T0 TEST FOUT / FOUT 0 0 0 Data Out – Last Bit SR FVCO ÷ N 0 0 1 HIGH FVCO ÷ N 0 1 0 FREF FVCO ÷ N 0 1 1 M Counter Output FVCO ÷ N 1 0 0 FOUT FVCO ÷ N 1 0 1 LOW FVCO ÷ N 110 S_CLOCK ÷ MS_CLOCK ÷ N 1 1 1 FOUT ÷ 4 FVCO ÷ N FOUT = ( ) x FXTAL 8 M N |
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