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24AA128EP Datasheet(PDF) 3 Page - Microchip Technology |
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24AA128EP Datasheet(HTML) 3 Page - Microchip Technology |
3 / 12 page © 1998 Microchip Technology Inc. DS21191B-page 3 24AA128/24LC128 TABLE 1-3 AC CHARACTERISTICS All parameters apply across the spec- ified operating ranges unless other- wise noted. Industrial (I): VCC = +1.8V to 5.5V Tamb = -40 °C to +85°C Automotive (E): VCC = +4.5V to 5.5V Tamb = -40 °C to 125°C Parameter Symbol Min Max Units Conditions Clock frequency FCLK — — — 100 100 400 kHz 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V Clock high time THIGH 4000 4000 600 — — — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V Clock low time TLOW 4700 4700 1300 — — — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V SDA and SCL rise time (Note 1) TR — — — 1000 1000 300 ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V SDA and SCL fall time TF — 300 ns (Note 1) START condition hold time THD:STA 4000 4000 600 — — — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V START condition setup time TSU:STA 4700 4700 600 — — — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V Data input hold time THD:DAT 0 — ns (Note 2) Data input setup time TSU:DAT 250 250 100 — — — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V STOP condition setup time TSU:STO 4000 4000 600 — — — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V WP setup time TSU:WP 4000 4000 600 — — — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V WP hold time THD:WP 4700 4700 1300 — — — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V Output valid from clock (Note 2) TAA — — — 3500 3500 900 ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V Bus free time: Time the bus must be free before a new transmission can start TBUF 4700 4700 1300 — — — ns 4.5V ≤ VCC ≤ 5.5V (E Temp range) 1.8V ≤ VCC ≤ 2.5V 2.5V ≤ VCC ≤ 5.5V Output fall time from VIH minimum to VIL maximum TOF 10 250 ns CB ≤ 100 pF (Note 1) Input filter spike suppression (SDA and SCL pins) TSP — 50 ns (Notes 1 and 3) Write cycle time (byte or page) TWC —5 ms Endurance 1M — cycles 25 °C, VCC = 5.0V, Block Mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s BBS or website. |
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