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24AA02ISN Datasheet(PDF) 5 Page - Microchip Technology |
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24AA02ISN Datasheet(HTML) 5 Page - Microchip Technology |
5 / 12 page © 1996 Microchip Technology Inc. DS21052F-page 5 24AA01/02 3.6 Device Address The 24AA01/02 are software-compatible with older devices such as 24C01A, 24C02A, 24LC01, and 24LC02. A single 24AA02 can be used in place of two 24LC01's, for example, without any modifications to software. The “chip select” portion of the control byte becomes a don't care. After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24AA01/02, followed by three don't care bits. The eighth bit of slave address determines if the master device wants to read or write to the 24AA01/02 (Figure 3-2). The 24AA01/02 monitors the bus for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a pro- gramming mode. FIGURE 3-2: CONTROL BYTE ALLOCATION Operation Control Code Chip Select R/W Read 1010 XXX 1 Write 1010 XXX 0 SLAVE ADDRESS X = Don’t care 101 0X X X R/W A START READ/WRITE 4.0 WRITE OPERATION 4.1 Byte Write Following the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24AA01/02. After receiving another acknowledge signal from the 24AA01/02 the master device will transmit the data word to be written into the addressed memory location. The 24AA01/02 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and dur- ing this time the 24AA01/02 will not generate acknowl- edge signals (Figure 4-1). 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24AA01/02 in the same way as in a byte write. But instead of generating a stop con- dition the master transmits up to eight data bytes to the 24AA01/02 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains con- stant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an inter- nal write cycle will begin (Figure 7-1). FIGURE 4-1: BYTE WRITE FIGURE 4-2: PAGE WRITE S P BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY S T A R T S T O P CONTROL BYTE WORD ADDRESS DATA A C K A C K A C K S P BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY S T A R T CONTROL BYTE WORD ADDRESS (n) DATA n DATA n + 7 S T O P A C K A C K A C K A C K A C K DATA n + 1 |
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