24C02C

DS21202A-page 4

Preliminary

© 1997 Microchip Technology Inc.

2.0

PIN DESCRIPTIONS

2.1

SDA Serial Data

This is a bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

Ω for 100 kHz, 2 kΩ for

400 kHz).

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are reserved

for indicating the START and STOP conditions.

2.2

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

2.3

A0, A1, A2

The levels on these inputs are compared with the cor-

responding bits in the slave address. The chip is

selected if the compare is true.

Up to eight 24C02C devices may be connected to the

same bus by using different chip select bit combina-

2.4

WP

This is the hardware write protect pin. It must be tied to

is enabled. If the WP pin is tied to Vss the hardware

write protection is disabled.

2.5

Noise Protection

is below 3.8 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

3.0

FUNCTIONAL DESCRIPTION

The 24C02C supports a bi-directional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, and a device

receiving data as receiver. The bus has to be controlled

by a master device which generates the serial clock

(SCL), controls the bus access, and generates the

START and STOP conditions, while the 24C02C works

as slave. Both master and slave can operate as trans-

mitter or receiver but the master device determines

which mode is activated.