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24C00T-SN Datasheet(PDF) 5 Page - Microchip Technology |
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24C00T-SN Datasheet(HTML) 5 Page - Microchip Technology |
5 / 18 page 2003 Microchip Technology Inc. DS21178D-page 5 24AA00/24LC00/24C00 4.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition (Figure 4-2). FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS FIGURE 4-2: ACKNOWLEDGE TIMING Note: The 24XX00 does not generate any Acknowledge bits if an internal program- ming cycle is in progress. (A) (B) (C) (D) (A) (C) SCL SDA START CONDITION ADDRESS OR ACKNOWLEDGE VALID DATA ALLOWED TO CHANGE STOP CONDITION SCL 9 8 7 6 5 4 3 2 1 123 Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. Receiver must release the SDA line at this point so the Transmitter can continue sending data. Data from transmitter Data from transmitter SDA Acknowledge Bit |
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