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ISL29033IROZ-EVALZ Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL29033IROZ-EVALZ Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 15 page ISL29033 7 FN7656.2 February 25, 2013 specification (2.25V to 3.63V), the following step is recommended: write 0x00 to register 0x00. Wait a few seconds, and then rewrite all registers to the desired values. A hardware reset method can be used, if preferred, instead of writing to the test registers. For this method, set VDD = 0V for 1 second or more, power backup at the required slew rate, and write the registers to the desired values. Power-Down To put the ISL29033 into a power-down state, the user can set [7 to 5] bits to 0 in Register 0. Or more simply, set all of Register 0 to 0x00. I2C Interface There are eight 8-bit registers available inside the ISL29033. The two command registers define the operation of the device. The command registers do not change until the registers are overwritten. The two 8-bit data read-only registers are for the ADC output. The data registers contain the ADC's latest digital output, or the number of clock cycles in the previous integration period (Figure 2). The ISL29033 I2C interface slave address is internally hard-wired as 1000100. When 1000100x, with x as R or W, is sent after the Start condition, the device compares the first 7 bits of this byte to its address, and matches. Figure 3 shows a sample one-byte read, and Figure 4 shows a sample one-byte write. The I2C bus master always drives the SCL (clock) line, while either the master or the slave can drive the SDA (data) line. Every I2C transaction begins with the master asserting a start condition (SDA falling while SCL remains high). The following byte is driven by the master and includes the slave address and the read/write bit. The receiving device is responsible for pulling SDA low during the acknowledgement period. Every I2C transaction ends with the master asserting a stop condition (SDA rising while SCL remains high). For more information about the I2C standard, please consult the Philips™ I2C specification documents. FIGURE 2. I2C TIMING DIAGRAM FIGURE 3. I2C READ TIMING DIAGRAM SAMPLE START W A A A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A A6 A5 A4 A3 A2 A1 A0 W A A A A D7D6 D5 D4 D3 D2D1 D0 13 5 7 13 57 12 3 4 5 6 9 2 4 6 STOP START SDA DRIVEN BY MASTER DEVICE ADDRESS SDA DRIVEN BY ISL29033 DATA BYTE0 REGISTER ADDRESS OUT DEVICE ADDRESS I2C DATA SDA DRIVEN BY MASTER SDA DRIVEN BY MASTER 24 68 9 2468 9 7 8 1 357 8 9 I2C SDA I2C SDA I2C CLK IN |
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