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27C256-15L Datasheet(PDF) 5 Page - Microchip Technology |
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27C256-15L Datasheet(HTML) 5 Page - Microchip Technology |
5 / 12 page © 1996 Microchip Technology Inc. DS11001L-page 5 27C256 FIGURE 1-2: PROGRAMMING WAVEFORMS TABLE 1-6: MODES Operation Mode CE OE VPP A9 O0 - O7 Read VIL VIL VCC XDOUT Program VIL VIH VH XDIN Program Verify VIH VIL VH XDOUT Program Inhibit VIH VIH VH X High Z Standby VIH XVCC X High Z Output Disable VIL VIH VCC X High Z Identity VIL VIL VCC VH Identity Code X = Don’t Care VIH VIL VIH VIL 13.0V(2) 5.0V 6.5V(2) 5.0V VIH VIL VIH VIL Address Data VPP VCC CE OE tDF and tOE are characteristics of the device but must be accommodated by the programmer VCC = 6.5 V ±0.25V, VPP = VH = 13.0V ±0.25V for express algorithm tPW tOES Address Stable tAH tDS tVPS tDF (1) tDH tOE (1) tAS Program Data Stable Data Out Valid Verify tVCS Notes: (1) (2) High Z 1.2 Read Mode (See Timing Diagrams and AC Characteristics) Read Mode is accessed when: a) the CE pin is low to power up (enable) the chip b) the OE pin is low to gate the data to the output pins For Read operations, if the addresses are stable, the address access time (tACC) is equal to the delay from CE to output (tCE). Data is transferred to the output after a delay from the falling edge of OE (tOE). |
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