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37LV65-P Datasheet(PDF) 6 Page - Microchip Technology

Part # 37LV65-P
Description  36K, 64K, and 128K Serial EPROM Family
Download  12 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

37LV65-P Datasheet(HTML) 6 Page - Microchip Technology

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37LV36/65/128
DS21109E-page 6
© 1996 Microchip Technology Inc.
TABLE 11-3:
PIN ASSIGNMENTS IN THE PROGRAMMING MODE
DIP/SOIC
Pin
PLCC Pin
Name
I/O
Description
1
2
DATA
I/O
The rising edge of the clock shifts a data word in or out of the
EPROM one bit at a time.
2
4
CLK
I
Clock Input. Used to increment the internal address/word
counter for reading and programming operation.
3
6
RESET/OE
I
The rising edge of CLK shifts a data word into the EPROM
when CE and OE are HIGH; it shifts a data word out of the
EPROM when CE is LOW and OE is HIGH. The address/
word counter is incremented on the rising edge of CLK while
CE is held HIGH and OE is held LOW.
Note 1: Any modified polarity of the RESET/OE pin is
ignored in the programming mode.
48
CE
I
The rising edge of CLK shifts a data word into the EPROM
when CE and OE are HIGH; it shifts a data word out of the
EPROM when CE is LOW and OE is HIGH. The address/
word counter is incremented on the rising edge of CLK while
CE is held HIGH and OE is held LOW.
510
VSS
Ground pin.
6
14
CEO
O
The polarity of the RESET/OE pin can be read by sensing the
CEO pin.
Note 1: The polarity of the RESET/OE pin is ignored while in
the Programming Mode. In final verification, this pin
must be monitored to go LOW one clock cycle after
the last data bit has been read.
717
VPP
Programming Voltage Supply. Programming Mode is entered
by holding CE and OE HIGH and VPP at VPP1 for two rising
clock edges and then lowering VPP to VPP2 for one more ris-
ing clock edge. A word is programmed by strobing the device
with VPP for the duration TPGM. VPP must be tied to VCC for
normal read operation.
820
VCC
+5 V power supply input.


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