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DS21109E-page 8

© 1996 Microchip Technology Inc.

FIGURE 11-3: ENTER AND EXIT PROGRAMMING MODES

FIGURE 11-4: PROGRAMMING CYCLE OVERVIEW (NO VERIFY UNTIL ENTIRE ARRAY IS

PROGRAMMED)

FIGURE 11-5: DETAILS OF PROGRAM CYCLE

CLK

DATA

CE

RESET/OE

CE

RESET/OE

CLK

Enter Mode

Exit Mode

High if RESET/OE configured

Low if RESET/OE configured

2 CLKS

**Load

Word 1

**Load

Word 2

**Load

Word 3

**Load

Word 4

**Load

Word 5

CE low to clear

data latches

Clock Increments

Address Counter

Enter

Programming

Mode

500

µs

Programming

Mode

500

µs

Programming

Mode

500

µs

Programming

Mode

500

µs

Programming

Mode

CLK

CE

RESET/OE

CEO

*

*

**

*

CLK

CE

RESET/OE

DATA

Load PROM

Internal

Data Latches

12

32 (Last Bit)

Clear PROM

Internal Data

Latches

Program

Pulse

Increment

Word

Counter

*Note: The programmer must float the data pin while

CE is low to avoid bus contention

*