© 1996 Microchip Technology Inc.

DS21109E-page 1

37LV36/65/128

FEATURES

• Wide voltage range 3.0 V to 6.0 V

• Maximum read current 10 mA at 5.0 V

• Standby current 100

µA typical

• Industry standard Synchronous Serial Interface/

1 bit per rising edge of clock

• Full Static Operation

• Sequential Read/Program

• Cascadable Output Enable

• 10 MHz Maximum Clock Rate @ 5.0 Vdc

• Programmable Polarity on Hardware Reset

• Programming with industry standard EPROM pro-

grammers

• Electrostatic discharge protection > 4,000 volts

• 8-pin PDIP/SOIC and 20-pin PLCC packages

• Data Retention > 200 years

• Temperature ranges:

-

Commercial: 0

°C to +70°C

- Industrial:

-40

°C to +85°C

DESCRIPTION

The Microchip Technology Inc. 37LV36/65/128 is a

family of Serial OTP EPROM devices organized inter-

nally in a x32 configuration. The family also features a

cascadable option for increased memory storage

where needed.

The 37LV36/65/128 is suitable for

many applications in which look-up table information

storage is desirable and provides full static operation in

the industry standard serial interface to the popular

RAM-based Field Programmable Gate Arrays (FPGA).

Advanced CMOS technology makes this an ideal boot-

strap solution for today's high speed SRAM-based

FPGAs. The 37LV36/65/128 family is available in the

standard 8-pin plastic DIP, 8-pin SOIC and 20-pin

PLCC packages.

Device

Bits

Programming Word

37LV36

36,288

1134 x 32

37LV65

65,536

2048 x 32

37LV128

131,072

4096 x 32

PACKAGE TYPES

BLOCK DIAGRAM

CLK

RESET/OE

CE

CEO

Vss

18

17

16

15

14

4

5

6

7

8

DATA

1

2

3

4

8

7

6

5

CEO

DATA

CLK

RESET/OE

CE

1

2

3

4

8

7

6

5

DATA

CLK

RESET/OE

CE

CEO

PDIP

SOIC

PLCC

OE

DATA

EPROM

ARRAY

CEO

ADDRESS

Counter

CLK

RESET/OE

CE

36K, 64K, and 128K Serial EPROM Family

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