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27C16A-15P Datasheet(PDF) 1 Page - Microchip Technology |
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27C16A-15P Datasheet(HTML) 1 Page - Microchip Technology |
1 / 8 page © 1996 Microchip Technology Inc. DS11125G-page 1 FEATURES • Fast Read Access Time—150 ns • CMOS Technology for Low Power Dissipation - 30 mA Active - 100 µA Standby • Fast Byte Write Time—200 µs or 1 ms • Data Retention >200 years • High Endurance - Minimum 104 Erase/Write Cycles • Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches • Data polling • Chip Clear Operation • Enhanced Data Protection -VCC Detector - Pulse Filter - Write Inhibit • Electronic Signature for Device Identification • 5-Volt-Only Operation • Organized 2Kx8 JEDEC Standard Pinout • 24-pin Dual-In-Line Package • 32-pin PLCC Package • 28-pin Thin Small Outline Package (TSOP) 8x20mm • 28-pin Very Small Outline Package (VSOP) 8x13.4mm • Available for Extended Temperature Ranges: - Commercial: 0˚C to +70˚C - Industrial: -40˚C to +85˚C DESCRIPTION The Microchip Technology Inc. 28C16A is a CMOS 16K non-volatile electrically Erasable PROM. The 28C16A is accessed like a static RAM for the read or write cycles without the need of external components. Dur- ing a “byte write”, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and auto- matically clear and write the latched data using an internal control timer. To determine when a write cycle is complete, the 28C16A uses Data polling. Data poll- ing allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications. PACKAGE TYPES BLOCK DIAGRAM A10 CE 21 20 19 VSS I/O2 14 13 12 OE NC A9 A8 22 23 24 NC NC A7 1 2 3 4 5 25 26 27 28 6 7 NC WE VCC A6 A5 A4 A3 I/O7 I/O6 I/O5 I/O4 I/O3 I/O1 I/O0 A0 A1 A2 18 17 16 15 11 10 9 8 OE NC A9 A8 NC WE Vcc NC NC A7 A6 A5 A4 A3 A10 CE I/07 I/06 I/05 I/04 I/03 Vss I/02 I/01 I/00 A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 • Pin 1 indicator on PLCC on top of package A6 A5 A4 A3 A2 A1 A0 NC I/O0 A8 A9 NC NC OE A10 CE I/O7 I/O6 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 • 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 V Vcc A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 SS I/O0 I/O7 Input/Output Buffers Chip Enable/ Output Enable Control Logic CE OE Data Protection Circuitry A10 Y Gating 16K bit Cell Matrix X Decoder Y Decoder A0 Data Poll Auto Erase/Write Timing VCC VSS WE L a t c h e s Program Voltage Generation 28C16A 16K (2K x 8) CMOS EEPROM This document was created with FrameMaker404 |
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