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93LCS66-SL Datasheet(PDF) 10 Page - Microchip Technology |
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93LCS66-SL Datasheet(HTML) 10 Page - Microchip Technology |
10 / 12 page 93LCS56/66 DS11181D-page 10 Preliminary © 1996 Microchip Technology Inc. FIGURE 2-13: PRDS TIMING CLK CS TCSL 0 DI BUSY • • • READY TWC DO 1 ONE TIME ONLY instruction. A PREN cycle must immediately precede a PRDS cycle. PE PRE 0 00 00 0 8 BITS OF "0" 3.0 PIN DESCRIPTION 3.1 Chip Select (CS) A HIGH level selects the device. A LOW level deselects the device and forces it into standby mode. However, a programming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought LOW during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. CS must be LOW for 250 ns minimum (TCSL) between consecutive instructions. If CS is LOW, the internal control logic is held in a RESET status. 3.2 Serial Clock (CLK) The Serial Clock is used to synchronize the communi- cation between a master device and the 93LCS56/66. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at HIGH or LOW level) and can be contin- ued anytime with respect to clock HIGH time (TCDD) and clock LOW time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a “Don't Care” if CS is LOW (device deselected). If CS is HIGH, but START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for START condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detection of a start condition the specified number of clock cycles (respectively LOW to HIGH transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (see instruc- tion set truth table). CLK and DI then become don't care inputs waiting for a new start condition to be detected. 3.3 Data In (DI) Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. 3.4 Data Out (DO) Data Out is used in the READ and PRREAD mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status informa- tion during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought HIGH after held LOW for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held LOW or HIGH during the entire WRITE or ERASE cycle. In all other cases DO is in the HIGH-Z mode. If status is checked after the WRITE/ERASE cycle, a pull-up resistor on DO is required to read the READY signal. 3.5 Program Enable (PE) This pin should be held HIGH in the programming mode or when executing the Protect Register program- ming instructions. 3.6 Protect Register Enable (PRE) This pin should be held HIGH when executing all Pro- tect Register instructions. Otherwise, it must be held LOW for normal operations. Note: CS must go LOW between consecutive instructions. |
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